1. Field of the Invention
The present invention generally relates to a device for processing data signals, a method thereof, and a device for multiplexing data signals.
2. Description of the Related Art
As shown in FIG. 1, an N:1 asynchronous data signal multiplexing device 9 multiplexes data signals, which are output from N numbers of interfaces 41, 42, . . . , 4n via signal lines 402, at an N:1 multiplexing circuit 3 and outputs an output data signal via a signal line 302.
Each of the interfaces 41, 42, . . . , 4n, in FIG. 1 stores a data signal for each of input data signals #1, #2, . . . , #n via signal lines 401 in a FIFO (First-In First-Out) memory 41 and an extracting circuit 42 extracts the data signal from the FIFO memory 41. Then, the data signals are output into the N:1 multiplexing circuit 3 via the signal lines 402. The N:1 multiplexing circuit 3 multiplexes the data signal output from the N numbers of the interfaces 41, 42, . . . , 4n and then outputs output data multiplexing the data signals via the signal line 302 and an output FP indicating a start of a time-division-multiplex period via a signal line 303.
As a process example in the N:1 asynchronous data signal multiplexing device 9, a case of outputting the data signals via the signal lines 402 from three interfaces 41, 42, and 43 is illustrated in FIG. 2. In FIG. 2, a numbered square represents each data signal processed in the three interfaces 41, 42, and 43. Also, the numbered squares are numbered in an input order. In this example, a data flow of the interface 41 begins from a data signal 1, a data flow of the interface 42 begins from a data signal 21, and a data flow of the interface 43 begins from a data signal 41. Each of the data signals is represented by using a numeral n indicated in the numbered squares.
In FIG. 2, data signals 1 through 4 are input each time the interface 41 outputs the output FP via the signal line 303 from the N:1 multiplexing circuit 3. Similarly to the interface 41, four data signals are input in each of the interfaces 42 and 43. Each of the four data signals is output by synchronizing with a synchronous clock 301 from each of the interfaces 41, 42, and 43. The N:1 multiplexing circuit 3 multiplexes the data signals output from each of the interfaces 41, 42, and 43, and outputs the output data carried by multiplexed data signals and the output FP.
Each input speed of inputting input data signals #1, #2, . . . , #n via respective signal lines 401 may be faster or slower than a clock speed of the synchronous clock 301 for sending the three data signals from the FIFO memory 41 to the N:1 multiplexing circuit 3. In this case, as shown in FIG. 2, four data signals are not always input to each of the interfaces 41, 42, and 43 every time the output FP is output via the signal line 302. That is, for example, five data signals may be input in a case of a faster input speed, or three data signals may be input in a case of a slower input speed.
For example, in a case in which only three data signals are input every time the output FP is output such as the interface 43 in FIG. 3, since the input speed of the FIFO memory 41 in FIG. 1 is faster than a clock speed for sending the three data signals from the FIFO memory 41 to the N:1 multiplexing circuit 3, the FIFO memory 41 becomes to lack the data signals. As a result, the FIFO memory 41 has nothing to send to the N:1 multiplexing circuit 3. Thus, one data signal is missing and cannot be output (failure of output data) in the N:1 multiplexing circuit 3.
On the other hand, in a case in which the input speed of inputting the data signals in the interface 43 is faster so that five data signals are input each time the output FP is output, since the input speed in the interface 43 is faster than the clock speed for sending the three data signals from the FIFO memory 41 to the N:1 multiplexing circuit 3, the FIFO memory 41 is saturated and the data signal overflows. Consequently, a slip phenomena occurs so that for example, a data signal 45 and a data signal 50 are not accumulated in the FIFO memory 41 and are therefore lost (cancellation of data signal).
In a time-division-multiplexing method in a conventional multiplexing device such as the N:1 asynchronous data signal multiplexing device 9, when there is a difference between the input speed of inputting the input data signal #1 via the signal lines 401 and the clock speed for sending the three data signals from the FIFO memory 41 to the N:1 multiplexing circuit 3, a data signal may be lost when the data signal is input and overflows, or a data signal may be missing when the data signal is to be multiplexed with other data signals.